Typical information processing systems include one or more video display terminals for providing a visual output of information. This visual output is in the form of an image. Such an image can be represented by any two dimensional array of image points represented by bit values stored at predetermined positions in a memory array made up of columns and rows of memory modules or chips. In order to process an imaging operation on the display terminal, it is required that an image or some part of an image be stored in a memory system which typically includes a memory array. Means must be provided for permitting access to sequences of image points along any row or column of the memory array. Such access to the memory array is required in order to write new information on the face of the display terminal as well as to refresh such information as required by a cathode ray tube (CRT) display terminal. Some other typical operations include rotating the image on the display as well as filling in a pattern on the display.
A problem that exists with raster scan displays, such as CRTs, which are all points addressable (APA), is updating the display memory array. In an all points addressable display system, hardware is required during memory update in order to perform detailed operations such as bit shift, mask, and merge.
One technique for implementing a refresh operation involves providing a two dimensionally addressed memory array in which no word or byte boundaries exist. That is, for each of the picture elements (pels) addressable in the memory array, there exists an X-Y address pair which uniquely locates that pel. Furthermore, whenever the array is accessed, multiple pels are written to or read from the memory array in a bit vector parallel to the direction of access to the array. A predetermined number of pels can be written into or read from the memory array in a single memory cycle beginning at any X-Y position without concern for what would ordinarily be the memory array's word boundary constraints.
With this addressing technique, hardware associated with the memory array recognizes which memory module in the array will be the starting point. The starting memory module is given the address n. Each memory module from the starting memory module to the module immediately following the starting point in the refresh operation is then given the address n+1. As a consequence, access to as many pels as there are memory modules in the refresh array in a single cycle is provided beginning at any X-Y pel position without concern for word boundaries.
A second technique for enhancing accessing of a memory array is the ability to support variable width write operations. To this end, a width control register can be provided to control the number of bits actually modified by a write cycle. Using this technique, once the starting point is identified for a given write cycle, a write operation is enabled to all the modules in the memory array. The modules in the memory array are written sequentially until the last module is reached. At this point, the write operation wraps back to the first module and continues until the specified width control register value is reached. Combining these two techniques provides the capability to access any number of pels up to the refresh array width at any arbitrary X-Y pel position. This is done as a bit vector parallel to the direction of access in a single cycle without regard to the memory array word boundaries.
U.S. Pat. No. 4,249,172 describes a display addressing system for accommodating vertically and horizontally varying entry points in a video memory. A memory link table has display memory addresses stored therein which point to first character bytes of video display rows. Logic circuitry transfers the memory address stored in the table to a memory address counter which, upon initialization, points to a first character byte of a first row of video information. The counter is then incremented to point to and thus display successive rows of video information.
In U.S. Pat. No. 4,442,503, assigned to the same assignee as the present invention, there is described a technique for enabling the two dimensional addressing of a display memory. The technique utilizes a storage unit for storing both blocks and rows of data and for retrieving rows of data. The storage unit operates in an interleaved mode, thus permitting two dimensional addressing over a plurality of separately addressable modules within the storage unit.
In an article entitled "Memory Systems for Image Processing", IEEE Transactions on Computers, Vol. C-27, No. 2, February 1978, pages 113-125, there is described an image supporting memory system which can be accessed in only the horizontal direction. The accessing of information in the horizontal direction in a memory array is quite typical in the prior art.
Heretofore, the accessing of information in a memory array for a display in both the horizontal and vertical directions has not been disclosed. The accessing of memory arrays in both a horizontal and vertical direction would greatly enhance memory array performance. For example, structures, such as lines on a display, that are represented as near colinear sequences of bits, which are either near vertical or near horizontal, can be written or refreshed as multiple bits per cycle. Structures, such as characters, which naturally tend to be taller than they are wide, can be written to a memory array as vertical slices instead of horizontal slices, thereby requiring fewer accesses to the memory array.